FPGA 101 : D Flip-flop

Introduction

D flip-flop is one of the most important element in digital logic design. It is multi-purpose element that can be used as register, synchronizer, pipeliner and memory. It is a synchronous component and it must be driven by a clock. This means operation of D flip-flop is basically constrained by a clock cycle time period, T. The way you connect the D flip-flop impacts the performance of overall design and its functionality as well. 

D Flip-flop with Synchronous Reset

always@(posedge clk)
begin
    if(reset)
        q <= 1'b0;
    else
    begin
        q <= d;
    end
end

D Flip-flop with Asynchronous Reset

always@(posedge clk or posedge reset)
begin
	if(reset)
		q <= 1'b0;
	else
	begin
		q <= d;
	end
end

D Flip-flop Symbol

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