Multiple clock domain with different clock frequencies usually found in complex design. It needs to take attention when we send data from one clock domain, to another clock domain’s flops due to the data might not successfully captured by flops. The flops then will fetch unpredictable outputs and this phenomenon called meta-stability.
The unpredictable outputs, means it probably outputs HIGH, LOW or stuck in voltage undefined region(in the middle between high and low). The most common situation when meta-stability happen in one of the data path is, the impacted system or IP will stop running and just hang there until reset it. For further reading you can refer to this good document : Altera
Example below show only a simple synchronizer and it does not cover all the scenario especially when the ‘Input’ is changing too fast and this example might not suitable to use as synchronizer. Besides, slower clock domain cross into faster clock domain or faster clock domain cross into slower clock domain will be another factor need to take care when design a synchronizer.
module sync_0 ( clk_a, data_in, clk_b, data_out ); input clk_a; input data_in; input clk_b; output data_out; reg sync_reg_a; reg [1:0] sync_reg_b; always@(posedge clk_a) begin sync_reg_a <= data_in; end always@(posedge clk_b) begin sync_reg_b <= sync_reg_a; sync_reg_b <= sync_reg_b; end assign data_out = sync_reg_b; endmodule