PWM, second-order low pass filter and DAC

ESP8266 SoC able to generate maximum 1KHz of 1024 steps PWM which ease us to design a DAC to provide reference voltage to current limiter circuit. The output voltage of V_{o} for following circuit can be determined as:

V_{o} = V_{pwm} * Duty Cycle

(1)

Where V_{pwm}_{ }is powered by 3.3V. In case R_{3} is absent and duty cycle set to 50%, theoretically output voltage would have 1.65V. Adding the Resistor R_{3 }further scale the output voltage to range 0-1V to represent 0-1A. Simulation below showing first-order output (blue line) has obvious ripple voltage and second-order output (red line) appears smoother.

Current limiter

Using another LM6142 to work as comparator to compare output voltage from current-to-voltage converter and PWM DAC. Voltage PWM DAC will be reference voltage to discipline PSU never output current more than this reference line. Whenever output voltage from current-to-voltage converter is higher than reference voltage (means current consumed by load is higher than expected), the comparator will output HIGH and this output voltage will be utilized later in voltage control circuit.

Simulation Scenario 1 : Load current is lower than reference voltage, output LOW

Simulation Scenario 2 : Load current is higher than reference voltage, output HIGH